Memory devices are used for a wide variety of applications in electronic devices, and are used to store different types of information, such as data or instructions. When loading instructions, it is important that the instructions are loaded and stored in a memory properly. One common application for employing memory is in programmable logic devices, such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD), for example. If instruction data loaded in a memory is corrupted, a circuit relying on the instruction data may not function properly. Therefore, it is important to verify that instruction data loaded to a memory is loaded and stored properly.
In conventional devices incorporating memory, an instruction side on-chip memory (ISOCM) interface is used primarily to fetch instructions from an instruction side Block RAM (ISBRAM) attached to it. Instructions may be loaded into the ISBRAM, either during configuration of a programmable logic device or using a dedicated register on a device control register (DCR) bus. As shown in FIG. 1, a conventional integrated circuit having memory comprises a processor 102 which issues a request to perform an instruction fetch starting from a specific ISOCM memory location. The ISOCM controller 104 detects this request, translates the request into control signals for ISBRAM 106, and controls the ISBRAM to perform an instruction fetch. Thus, the ISOCM controller receives instructions from the ISBRAMS via BUS B, and then sends the instructions on the BUS A, so that the processor can execute the instruction.
When there is a write access on BUS C (i.e. the processor gives signals indicating that it will write instructions into ISBRAM using the DCR bus), the ISOCM controller detects the write instructions, and translates them to perform an instruction write. Along with ISBRAM specific, write control signals, the data to be written to ISBRAM also gets transferred onto BUS D. Accordingly, a user can use DCR access to write into the ISBRAM array in such conventional devices. For each write to the ISBRAM, the ISOCM controller writes into the ISBRAM, and increases the address for ISBRAM address, as will be described in more detail below with respect to FIG. 3.
As shown in FIG. 2, a conventional DCR multiplexer 202 selects data from one of a plurality of instruction side registers. In particular, an ISFILL register 204 couples data stored in the ISFILL register to DCR multiplexer 202. Similarly, an ISINIT register 206 couples the initial address to DCR multiplexer 202. An ISCNTL register 208 couples any required control signals to DCR multiplexer 202. Finally, an ISARC register 210 is a DCR register that stores 8 bit of address specified by user. It is used to compare with the upper 8 bits of address that the processor provides to the ISOCM controller. In the ISOCM controller, the upper 8 bits of the processor address are compared with the 8-bits in ISARC. If they match, that piece of the address sent by the processor is within the ISOCM memory space, and the controller will let the instruction side on-chip memory respond to the processor commands. Otherwise, the ISOCM will just ignore the command.
As shown in FIG. 3, a conventional circuit for writing an address to the ISBRAM is shown. In particular, an initial address received from the DCR is coupled to a multiplexer 302. The multiplexer receives a load ISINIT register signal to select to receive either the address from the DCR or an output of a second multiplexer 304, which selects an address which may be incremented by 1, as a result of the Increment by 1 block 306. That is, multiplexer 304 receives a Write ISFILL Command from the processor to determine whether the address is to be retained in the ISINIT Register, or the address is to be incremented by 1.
In order to make sure that the instruction contents of the ISBRAM are written acurately, the instruction data must be verified. In conventional devices incorporating memory devices, it is difficult to provide a software based debugging of the memory device. As processor executes instructions, if a program results in an error or illegal instruction, it is hard for a user to debug since the instruction is fetched from ISBRAMs and fed to the instruction register by way of a bus for fetching instructions. The only known method to read contents of a memory (e.g. BRAM) that serves as an instruction side on-chip memory in an FPGA is using soft FPGA IP based techniques. That is, a user would typically access the contents of the memory by way of a processor local bus, and read the contents through an arbiter and a BRAM controller. However, such techniques, which are well known in the art, result in lower performance and high area overhead. Since it is not very practical to implement soft IP based solutions, an FPGA bitstream read back mechanism is often used to read the contents of ISBRAMs. However, such a bitstream read back mechanism cannot be used with the software debugging tools.
Accordingly, there is a need for a circuit for and method of accessing instruction data written to a memory to read back and verify the instruction contents of a memory.